This invention generally relates to electronic systems and in particular it relates to opamps with a dynamic slew-rate booster.
The analog core of pipeline high-speed, high-resolution analog-to-digital converters (ADCs) requires the adoption of opamps both very fast and with high gain. While the prior art opamp designs often seem to be optimized if inspected via AC simulations, these opamps reveal an insufficient load charging performance at a subsequent transient analysis, and do not settle properly in the few nanoseconds available. This shortcoming has been verified both on rising and falling transitions of the differential output of opamps using active loads.
The prior art approach to opamp speed-up encompasses increasing the current in the stage (leads to swing and power consumption issues), enlarging the transistors"" size (area occupation, and parasitics worsening), or shrinking the external capacitors (conflicts with kT/C noise floor limits). Moreover, bulky output buffer stages harm the stability of the opamp loop.
An opamp with a slew rate booster includes a first high side transistor coupled to a first differential output node; a second high side transistor coupled to a second differential output node; a first booster circuit coupled to the control node of the first high side transistor; a second booster circuit coupled to the control node of the second high side transistor. The opamp exploits the gate control available on the high side transistors 23 and 26. During the charge-discharge differential transient of the load capacitances 58 and 60, the circuit increases the current given by the high side transistor 23 or 26 that is pulling up its output OUTxe2x88x92 or OUT+, and reduces by the same amount the current provided at the other output OUT+ or OUTxe2x88x92 that is being pulled down by a low side driver 43 or 40. The gate control is accomplished through a simple, symmetrical capacitor-resistor network that implements a basic differentiator.